In a synchronous semiconductor memory device, which is one of synchronous semiconductor devices, a signal representing a command or data supplied externally to the synchronous semiconductor memory device is captured into the synchronous semiconductor memory in synchronization with an external clock signal such as a system clock supplied externally to the synchronous semiconductor memory device. A signal representing data read from the synchronous semiconductor memory device is outputted in synchronization with the external clock signal. The synchronous semiconductor memory device includes an internal clock generation circuit that generates an internal clock signal, based on the received external clock signal. One of circuits that is arranged in the synchronous semiconductor memory device and is driven by a clock signal, operates in synchronization with the internal clock signal generated by the internal clock generation circuit. Due to a wiring delay in the semiconductor device or the like, a timing skew is generated between the internal clock signal and the external clock signal. For this reason, in the synchronous semiconductor memory device, a synchronizing circuit such as a DLL (Delay Lock Loop: delay lock loop) circuit is employed to synchronize the internal clock signal with the external clock signal. The DLL enables the output data which is synchronized with the internal clock signal to be outputted in synchronization with the external clock signal.
Patent Document 1 discloses a synchronous semiconductor memory device including a read information signal generation circuit, a delay circuit, and a latency control signal generation circuit. The delay circuit delays a read information signal (COSR) outputted from the read information signal generation circuit by one cycle of a first clock (PCK), in response to the first clock. The first clock is delayed from a system clock (CLK) applied from outside the synchronous semiconductor memory device just by a predetermined phase difference. The latency control signal generation circuit generates a latency control signal for determining a generation point of time of output data. The latency control signal is configured to sample the delayed read information signal (COSRD) during a first logic state segment (such as a High state segment) of a second clock (CLKDQ) in response to the second clock (CLKDQ) that advances from the system clock (CLK) by a predetermined phase difference, and then delay the sampled signal, thereby generating the latency control signal. FIG. 5 in Patent Document 1 discloses a method of sampling the delayed read information signal (COSRD) during a C2 cycle in order to ensure an operating margin (frequency margin and sampling margin of the system clock) when the output data read from a memory element in synchronization with the internal clock signal is timing-adjusted to data synchronized with the external clock signal. When the frequency of the system clock is further increased, a sufficient operating margin cannot be ensured in the circuit and the method described in Patent Document 1.
FIG. 12 is a diagram schematically showing the configuration of a prototype example of a synchronous semiconductor memory. Referring to FIG. 12, a memory cell array 70 includes a plurality of memory cells MC in an array form at intersections between word lines WL and bit lines BL. Though no particular limitation is imposed, it is assumed below that each memory cell MC is a DRAM (Dynamic Random Access Memory) cell. In this cell, a word line is connected to a gate of the memory cell MC, one of a source and a drain of the memory cell MC is connected to a bit line, the other of the source and the drain of the memory cell MC is connected to a capacitor, and data is held in the capacitor. The synchronous semiconductor memory may be of course an SRAM (Static Random Access Memory).
A row system control circuit 41 latches a row address of an address signal received at an address terminal, and supplies the latched row address to a row decoder 71 and generates row system control signals.
A column system control circuit 51 latches a column address of the address signal, and supplies the latched column address to a column decoder 73 and generates column system control signals.
The row decoder 71 decodes a row address signal to select a word line. The selected word line is driven by a word driver not shown.
In the case of the DRAM memory cell, each of sense amplifiers (SAs) 72 amplifies data read onto the bit line BL connected to the memory cell MC connected to the selected word line. When refreshing is performed, the sense amplifier further writes the data amplified into the memory cell MC to restore the data in the memory cell MC.
The column decoder 73 decodes the column address of the received address signal and connects the sense amplifier 72 of a selected column to an input/output line not shown (such as a local input/output line). In the prototype example shown in FIG. 12, as an input/output line (IO line) configuration, a hierarchical input/output line configuration is employed. This configuration includes local input/output lines, each of which is connected to the sense amplifier 72 selected via a column switch (not shown) which is turned on by She column decoder 73, and main input/output lines, each of which is provided in common to local input/output lines. Bach of the main input/output lines is connected to one selected LIO line through a switch that is turned on.
Each of data amplifiers 74 is connected between the main input/output line (MIO) and a read/write bus RWBS1. The data amplifier 74 includes a read amplifier (not shown) for amplifying read data transferred from the sense amplifier 72 connected to the selected bit line BE to the main input/output line (MIO) through the local input/output line to drive the read/write bus RWBS1 and a write amplifier (not shown) for receiving and amplifying write data transferred to the read/write bus RWBSI to drive the main input/output line (MIO).
A data input/output unit 85 includes (n+1) output buffers (not shown) for respectively driving data input/output terminals DQ0 to DQn with the read data (bit data) and a retiming register (not shown) for timing-adjusting the bit data output to the DQ terminals from the output buffers to enhance timing accuracy. The retiming register is clocked by an output clock signal LCK1 of a DLL 100A which will be described later. The data input/output unit 85 further includes in (n+1) receiver circuits (not shown) for respectively receiving bit data (write data) supplied to the data input/output terminals DQ0 to DQn. When the receiver circuits receive data, circuits of the output buffers are set to be output-disabled (with outputs thereof brought into a high-impedance state).
Parallel bit data (such as 4-bit parallel data) that have been read lo a plurality of the MIO lines (such as four MIO lines) in parallel from the memory cell array 70, amplified by a plurality of the data amplifiers 74 (such as four data amplifiers 74), and then outputted in parallel to the read/write bus RWBSI are temporarily supplied to a FIFO control unit 84, and are then outputted to the DQ terminal after a predetermined latency through the data input/output unit 85. In a synchronous DRAM (SDRAM), the predetermined latency corresponds to a CAS latency, which is the number of clock cycles from input of a READ command to output of first-bit data from the DQ terminal.
A command decoder 31 receives a command signal and predetermined bits of the address signal, and supplies a result of decoding to a control logic circuit 32. Though not limited thereto, as a command signal, a combination of signal values of a /CS (chip select) signal, a RAS (row address strobe) signal, a /CAS (column address strobe) signal, and a /WE (write enable) signal and a predetermined address signal bit field(s) are received as a command and its parameters.
The control logic circuit 32 receives a result of decoding by the command decoder 31 and generates, in accordance with an input command, various control signals related to read control, write control, refreshing, and the like to control the column system control circuit 51, the sense amplifiers (SAs) 72, the data amplifiers 74, and the like.
Parameters that are used to specify an operation mode of the synchronous semiconductor memory (such as a burst length) are set in a mode register 61 by a mode register set command received as one of the command signals.
A clock generation circuit 21 differentially receives complementary clock signals CK and /CK supplied from the outside and receives a clock enable signal CKE and generates an internal clock signal (internal reference clock signal) ICLK to supply the internal clock signal ICLK in a single-ended form to an internal circuits of the device. Operations of the internal circuits including a sequential circuit such as a flip-flop are performed in synchronization with the internal clock signal ICLK. When the clock enable signal CKE is Low, an operation at a subsequent rising edge of the clock CK (falling edge of the clock /CK) is ignored, so that the operations in the internal circuits driven by the internal clock signal ICLK are not performed. When the clock enable signal CKE is High, the clock generation circuit 21 outputs the internal clock signal ICLK synchronized with the clock signals CK and /CK.
The DLL (Delay Lock Loop: delay lock loop) 100A outputs a clock signal LCLK1 delayed from the external complementary clock signals CK and /CK by a predetermined delay time.
The DLL 100A includes an initial-stage circuit 101, a delay circuit 102, a DQ replica 105A, a phase detector circuit 104, and a delay control counter 103A. The initial-stage circuit 101 includes a receiver circuit (not shown) that differentially receives the external clock signals CK and /CK to provide a single-ended output. The delay circuit 102 receives the clock signal outputted from the initial-stage circuit 101, delays and outputs the clock signal. A delay time of the delay circuit 102 can be variably set. The DQ replica 105A includes a buffer (also referred to as a “dummy buffer”) equivalent to each output buffer not shown in the data input/output unit 85. The DQ replica 105A receives the clock signal LCK1 outputted from the delay circuit 102, and delays the clock signal LCK1 by a delay amount corresponding to a propagation delay time of the output buffer to output the delayed the clock signal LCK1. The phase detector circuit 104 detects a phase difference between the output signal of the DQ replica 105A and the external clock signals CK and /CK. The delay control counter 103A receives a result of the phase detection (up/down signal corresponding to a phase advance/delay) by the phase detector circuit 104 to increment or decrement a count value, thereby functioning as an integrator. The delay lime of the delay circuit 102 is determined, based on the count value of the delay control counter 103A. When the delay circuit 102 is composed by a VCDL (Voltage Controlled Delay Line) whose delay is varied by a control voltage, the count value (digital value) of the delay control counter 103A is converted to an analog voltage by a DA converter not shown, and is applied to the VCDL of the delay circuit 102.
When a rising phase of the signal obtained by delaying the clock signal LCK1 by a time corresponding to the delay time of the DQ replica 105A is aligned with a rising phase of the external clock signal CK, the DLL 100A is in a locked state. In this case, the phase detector circuit 104 outputs a phase comparison result that indicates a phase advance or a phase delay. The delay control counter 103A counts one count up or down in accordance with the phase comparison result. A delay obtained by averaging count values of the delay control counter 103A is then set in the delay circuit 102. When the external clock signals CK and /CK and the output of the DQ replica 105A are phase-aligned during when the DLL 100A is in a locked state, a rise timing of the output clock signal LCK1 of the DLL 100A advances from a rise timing of the external clock signal CK, by a time corresponding to the delay time of the DQ replica 105.
An adjustment delay circuit 91 outputs to an output latency control circuit 80A a signal LCLK2 obtained by adjusting a delay of the output LCLK1 of the DLL 100A, corresponding to the delay of the DQ replica 105A.
A signal RCMD is an internal read command signal, which is a control signal outputted from the control logic circuit 32 in synchronization with the internal clock signal ICLK. When an input command has been decoded by the command decoder 31 and then has been found to be a read command, the internal read command signal RCMD is outputted from the control logic circuit 32 that has received a result of decoding by the command decoder 31.
The output latency control circuit 80A includes an output control circuit 81A that receives the internal read command signal RCMD and the signal LCLK2 obtained by adjusting the delay of the output signal LCLK1 of the DLL by the adjustment delay circuit 91 and a latency control unit 82 that receives a control signal OE0 outputted from the output control circuit 81A to perform latency control.
The output control circuit 81A includes a logical operation circuit that performs a logical operation on the signal LCLK2 and the internal read command signal RCMD. Though not limited thereto, the output control circuit 81A includes an AND circuit that performs the following AND operation on the signal LCLK2 and the internal read command signal RCMD:    OE0=AND (LCLK2, RCMD)
Responsive to the activation (High) of the signal OE0 from the output control circuit 81A, the latency control circuit 82 activates an output enable rise signal (OER) for clock cycles corresponding to a burst length BL (corresponding to four clock cycles when BL=8, for example) from a rising edge of the internal clock signal ICLK and activates an output enable fall signal (OEF) for the clock cycles corresponding to the burst length BL (corresponding to four clock cycles when BL=8, for example) from a falling edge of the internal clock signal ICLK.
The FIFO control unit 84, which is a buffer circuit in a read system, includes a memory FIFO (First In and First Out) of a first-in-first-out type, a control unit (not shown) that controls reading from and writing to the memory FIFO, and a parallel-to-serial conversion circuit (not shown) that converts parallel bits outputted from the memory FIFO to serial bits. The FIFO control unit 84 writes parallel bit data (e.g. 4-bit parallel data) read to the read/write bus RWBSI to the memory FIFO (not shown) in parallel in response to a generated write clock signal (signal FIFO_INPUT synchronized with the internal clock signal ICLK, which will be described later, for example), reads parallel data written in the FIFO memory in parallel in response to a generated read clock(signal FIFO_OUTPUT synchronized with the internal clock signal ICLK, for example, which will be described later), converts the parallel bit data to a serial bit signal by the parallel-to-serial conversion circuit (not shown), and serially transfers the serial bit signal to (he data input/output unit 85 at a double data rate (the internal clock signal ICLK, for example, is used as a clock for the transfer).
The data input/output unit 85 captures the bit data serially transferred from the FIFO control unit 84 into a register (not shown), using the output clock signal LCLK1 of the DLL 100A to perform timing adjustment, and supplies the bit data to the output buffer (not shown). The output buffers (not shown) drive DQ terminals (wirings). 8-bit burst data D0 to D7 which are outputted from the FIFO control unit 84 to DATA0 which is an LSB (Least Significant Bit) output of the FIFO control unit 84, are supplied to the output buffer (not shown) whose output is connected to the data terminal DQ0 at the double data rate, in response to a rise and a fall of the clock signal LCLK1. and are sequentially output to the DQ0 terminal from the output buffer.
A rising edge of the clock signal LCLK1 outputted from the DLL 100A advances in time from a rising edge of the external clock signal CK by the propagation delay time (propagation delay time of the output buffer). The output timing of even-numbered data (D0, D2, D4, D6) supplied to the output buffer (not shown) to the DQ0 terminal in synchronization with the rising edge of the clock signal LCLK1 coincides with the rise timing of the external clock signal CK. Further, in case a duty ratio of the clock signal is 50%, the output liming of odd-numbered data (D1, D3, D5, D7) supplied to the output buffer (not shown) to the DQ0 terminal in synchronization with the falling edge of the clock signal LCLK1 coincides with the fall timing of the external clock signal CK. For simplicity of explanation, FIG. 12 shows an example in which the synchronous semiconductor memory includes one DLL 100A and phase comparison is made between rising edges of the external clock signal CK and the output of the DQ replica. A configuration may be used where the synchronous semiconductor memory includes two DLLs, signals respectively obtained by delay locking the rising and falling edges of the external clock signal CK are generated, and these signals are synthesized, for output.
Clock change-over from the internal clock signal ICLK to the clock signal LCLK2 is substantially performed at the output control circuit 81A.
The internal read command RCMD is outputted from the control logic circuit 32 to the output control circuit 81A in synchronization with the internal clock signal ICLK. The output control circuit 81A, responsive to the internal read command RCMD, generates the output control signal OEO in synchronization with the clock signal LCLK2.
[Patent Document 1]
JP Patent Kokai Publication No. JP2002-230973A, which corresponds to U.S. Pat. No. 6,643,215B2
Following describes an analysis of the prototype example in FIG. 12 by the inventor of this application.
A clock timing skew may occur between respective clock timings of the signal LCLK2 obtained by delaying the output signal LCLK1 of the DLL 100A by the adjustment delay circuit 91 and the internal clock signal ICLK. The reason for the occurrence of this skew is that process dependencies are different between the internal clock signal ICLK from the clock generation circuit 21 and the clock signal LCLK2 in terms of a power supply voltage characteristic, a temperature characteristic, and so forth. The clock signal LCLK2 is obtained by delaying the output LCLK1 of the DLL 100 including in a loop thereof the DQ replica 105A that is driven by a power supply voltage corresponding to the signal amplitude of each DQ terminal.
Basically, output control by the output control circuit 81A or output control of the signal OE0 is performed by one clock cycle tCK. That is, the internal read command, signal RCMD is outputted from the control logic circuit 32 in synchronization with the internal clock signal ICLK, and a period during which the internal command signal RCMD is asserted is set to be less than one clock cycle tCK. In an SDRAM DDR 3, the one clock cycle tCK becomes approximately Ins (nanosecond). Accordingly, a timing margin becomes crucial, so that a timing failure lends to occur.
When the power supply voltage decreases, the delay time of the DQ replica 105A increases. Consequently, a time difference between an effective edge (rising edge) of the output signal LCLK1 of the DLL 100A and an effective edge (falling edge) of the external clock signal CK increases. That is, a rise timing of the signal LCLK1 is temporally further in advance of a rise timing of the external clock signal CK. On the other hand, when the power supply voltage decreases, a delay of the internal clock signal ICLK outputted from the clock generation circuit 21 increases. Then, due to the delay of the internal clock signal ICLK, a timing at which the internal read command signal RCMD is asserted is delayed.
As a result, a timing at which the signal LCLK2 obtained by delaying the output signal LCLK1 of the DLL 100A by the adjustment delay circuit 91 rises from Low to High, becomes earlier in the output control circuit 81A (AND circuit). A timing at which the internal read command signal RCMD rises from Low to High is delayed. A period during which a High period of the signal LCLK2 and a High period of the internal read command signal RCMD overlap in time with each other may be narrowed (or may be extremely narrowed). Alternatively, the High period of the signal LCLK2 and the High period of the internal read command signal RCMD may not overlap at all. Consequently, the signal OE0 may not be properly outputted from the output control circuit 81A, thereby causing a malfunction. A pulse width of the signal OE0 may be narrowed into a glitch, causing a setup/hold time error in a subsequent-stage circuit. Alternatively, a pulse of the signal OE0 may not be output, thereby causing a malfunction in a subsequent-stage circuit.
When the one clock cycle tCK is further shortened, a leading edge of a High pulse of the signal LCLK2 in the next cycle may overlap in time with a trailing edge of a High pulse of the internal read command signal RCMD. In this case, the signal OE0 may be erroneously outputted from the output control circuit 81A at a timing at which the signal OEO should not be output according to the design specification.
As described above, a timing margin in the configuration shown in FIG. 12 is crucial. The output control signal OE0 may not be outputted from the output control circuit at a proper timing, so that a malfunction may occur.